CPU Fetch-Decode-Execute Simulation | onlinecstutor.com

onlinecstutor.com A-Level · CPU Architecture

ALU

—

ACC

0

CIR

—

CU

Control Unit

PC

0

SR

—

MBR

—

MAR

—

CPU

RAM

Ready. Set inputs A and B, then press Step to begin.

Input A

Input B

Output

—

Speed: